The present invention relates to a charged beam exposure technique in lithography of the manufacture of electronic devices such as semiconductor devices and, more particularly, to a mask used in exposing a wafer with a charged beam, a charged beam exposure apparatus using this mask, and a device manufacturing method employing this apparatus.
In mass production of semiconductor memory devices, an optical stepper having high productivity has been used. In production of next-generation memory devices of 1-gigabit or 4-gigabit DRAMs having a line width of 0.2 xcexcm or less, the high-productivity electron beam exposure method having high resolving power is expected as one of the exposure techniques that replace the optical exposure system.
The conventional electron beam exposure method is mainly performed using a Gaussian beam or variable shaped beam system, and accordingly has a low productivity. Therefore, the electron beam exposure method has been used in applications such as mask drawing, research and development of VLSIs, and exposure of ASIC devices on small-lot production, by effectively using the characteristics of the excellent resolving performance of the electron beam.
To apply the electron beam exposure method to mass production in this manner, how to increase its productivity is a significant problem. In a conventional electron beam exposure apparatus, the exposure region of an electron optical system that can be exposed by one shot is extremely smaller than the exposure region of the projection optical system of an optical exposure apparatus. To expose the wafer entirely takes a very long period of time since the distances of electronic scanning and mechanical scanning become longer than in the optical exposure apparatus, resulting in an extremely low throughput. To increase the throughput, either the electronic scanning speed and the mechanical scanning speed must be further increased greatly, or the one-shot exposure region must be enlarged greatly.
As one of methods that solve this problem of throughput increase while maintaining a necessary resolving power, a following method is discussed. According to this method, a circuit pattern to be exposed onto a silicon wafer is formed on a mask. An electron beam having an enlarged exposure region irradiates the mask, so that the mask pattern is projected onto the wafer. As the electron beam having an enlarged exposure region, one having a rectangular spot is usually used. In the electron beam exposure apparatus shown in FIG. 18, the beam has an arcuate spot to decrease the curvature of field, so that the exposure region is further increased, thereby solving the above problem.
FIG. 18 shows an electron gun 101, an electron beam 602, an axis 120 of an electron optical system, a condenser lens 103, an aperture 104, a mask 605, an aberration correcting optical system 107, electron lenses 108A and 108B, a scattered electron limiting aperture 111, a wafer 114, a moving direction 121 of the mask stage at a certain time point, a moving direction 122 of the wafer stage at a certain time point, an aperture opening 201, an electron beam irradiated region 202 on the mask, a device pattern 603 on the wafer, and a region 604 to be irradiated with an electron beam by wafer moving.
The electron beam mask used in this electron beam exposure apparatus has a circuit pattern the size of which depends on the magnification of the projection system of the electron beam exposure apparatus and is usually twice to 5 times that of the circuit pattern on the silicon wafer. For example, it is said that a circuit pattern corresponding to one 4-gigabit DRAM chip requires an area of about 20 mmxc3x9735 mm. The area of the circuit pattern on the mask used for exposing this circuit pattern is 80 mmxc3x97140 mm when the magnification of the projection system is xc2xc. It is difficult to form a circuit pattern of this size on one thin film portion 605a surrounded by a reinforced portion 606a on the mask, as shown in FIG. 19A, with a sufficiently large strength and sufficiently high precision. Hence, as schematically shown in FIG. 19B, this circuit pattern is divisionally formed on a plurality of thin film portions 605b into a plurality of chip patterns M1 to M9, and the respective divided chip patterns are reinforced with a rectangular bar portion 606b (the portion will be referred to as a strut hereinafter).
To expose the chip patterns M1 to M9 divided on the mask onto the wafer, as shown in FIG. 20A, the mask stage is moved with respect to an electron beam 602a having a fixed irradiation position. The group of divided chip patterns on the mask, which is to be irradiated with the electron beam 602a by one moving operation of the mask stage in an X direction shown in FIG. 20A, is called xe2x80x9cdivided chip patterns on a stripexe2x80x9d. For example, the divided chip patterns M1, M2, and M3 exist on the same stripe. The mask stage moves in the direction of an arrow A such that the electron beam 602a moves across the respective stripes. In synchronism with this, the wafer stage is moved in the direction of an arrow B (FIG. 20B). When the electron beam is deflected by a deflector not shown in FIG. 18, the patterns are stitched to each other such that the bars among the divided patterns on the same stripe on the mask do not appear on the reduced pattern on the wafer 114. When the mask stage and wafer stage are moved up to the first pattern on each stripe, the patterns among the stripes are stitched to each other such that bars among the stripes on the mask do not appear on the reduced pattern on the wafer 114. The divided chip patterns M1, M2, . . . on the mask in FIG. 20A are reduced on the wafer 114 of FIG. 20B and are stitched to each other as patterns W1, W2, . . . . When the above operation is repeated, a plurality of device chip patterns 603, each consisting of the plurality of divided chip patterns and corresponding to one chip, are exposed onto the wafer 114.
The following problem, however, arises. That is, if the electron beam width is larger than the width of struts among the divided patterns on one stripe on the mask, the total dose varies, and the position of the transfer pattern is partially shifted. This problem will be described using a rectangular beam spot with reference to FIG. 21.
Referring to FIG. 21, reference numeral Bw1 denotes the width of a rectangular cross-sectional electron beam 602c on the mask 605; s1, the width of a strut between divided patterns within one stripe on the mask; and sw1, the length of a portion on the wafer which corresponds to a strut width s1 of the mask. Reference numerals M1 to M9 denote respective divided patterns on the mask; and W1 to W3, transfer patterns on the wafer that correspond to the divided patterns M1 to M3 of the mask.
Referring to FIG. 21, chart I schematically shows the distribution of an exposure dose on the wafer obtained when transferring the divided pattern M1 on the mask 605. In chart I, the axis of abscissa represents the positions of the transfer patterns W1, W2, and W3 on the wafer that correspond to the divided patterns M1, M2 and M3 on the mask during exposure, and the axis of ordinate represents the dose at each position. If the beam width on the mask is larger than the strut width, i.e., if Bw1 greater than s1, the divided pattern M2 is partly exposed undesirably immediately before exposure of the pattern M1 is ended. Accordingly, as shown in chart I, the divided pattern M2 which should not be originally transferred is partly transferred to a position shifted from the transfer pattern W1 by sw1 within the transfer pattern W2 on the wafer. Similarly, when exposing the divided pattern M2, as shown in chart II, the divided pattern M3 is partly transferred to a position shifted from the transfer pattern W2 by sw1 within the transfer pattern W3 on the wafer. Chart IV shows the total dose at positions on the wafer, which correspond to stripe 1, when the divided patterns M1, M2, and M3 on stripe 1 are exposed. As is apparent from chart IV, when the beam width is larger than the strut width on the mask, the total dose varies on the mask, and the position of the transfer pattern is partly shifted, thus degrading the pattern precision.
The present invention has been made in view of the problems of the prior art, and has as its object to provide a charged beam projection mask with which variations in exposure dose and a positional error of the pattern projected on the mask are prevented to improve the pattern precision, a charged beam exposure apparatus using this mask, and a device manufacturing method suitable for manufacturing a device by this apparatus.
It is another object of the present invention to provide a charged beam projection mask with which the throughput is increased and the exposure precision is increased and which can be manufactured easily, a charged beam exposure apparatus using this mask, and a device manufacturing method suitable for manufacturing a device by this apparatus.
In order to achieve the above objects, the present invention has the following constitution. More specifically, in the projection mask, the charged beam exposure apparatus using this mask, and the device manufacturing method suitable for manufacturing a device by this apparatus according to the present invention, the width (scanning direction) of struts separating a plurality of divided patterns on the mask is larger than the beam width on the mask. When the strut width is set larger than the beam width on the mask in this manner, variations in exposure dose and a positional error of a pattern projected on the wafer are prevented to prevent degradation in pattern precision on the wafer.
Furthermore, in the present invention, the shape of part of each strut separating the plurality of regions matches the shape of the charged beam. In particular, when the charged beam has an arcuate spot, the strut portion separating the respective separated regions in one row on the mask is arcuate. Therefore, the distance between the divided regions decreases, and accordingly the mask area and mask stage moving distance decrease. As a result, the throughput is increased, the mask manufacture is facilitated, and the pattern precision is improved. It is desirable if the following means are also provided.
More specifically, if the radius of the arcuate cross-sectional electron beam and the radius of the arcuate strut are set to be equal to each other, a further increase in throughput can be obtained.
If the divided pattern width is set to be 0.9 times or less the diameter of the arcuate cross-sectional charged beam, the mask precision can be improved.
The divided pattern width and length are determined on the basis of a precision map experimentally obtained, so that pattern precision can be improved.
When the divided pattern widths are set to be almost equal to each other, the number of stripes is reduced, and the throughput is increased.
When the division boundary of divided patterns facing a strut bar has an arcuate shape, the throughput is increased.
When the radius of the division boundary of the arcuate divided patterns and the radius of an arcuate strut are set to be equal to each other, a further increase in throughput can be achieved.
In an exposure apparatus for sequentially exposing a mask, on which the pattern to be exposed is divided into a plurality of regions, with an arcuate cross-sectional charged beam, thereby projecting the pattern onto a photosensitive substrate, if the width of the charged beam on the mask is set smaller than the width of the struts separating the plurality of regions, and if a charged beam having a smaller spot diameter than the width of the struts is scanned in a direction along which the struts separating the plurality of regions are arranged, to sequentially expose the patterns, the precision of the transfer pattern is improved.
In particular, when a non-linear strut is arcuate to match the spot shape of the arcuate cross-sectional charged beam, in terms of an increase in throughput, the radius of the arc of the charged beam is preferably substantially equal to the radius of the arc of the struts, and the bending direction of the arc of the charged beam is preferably set to be in substantially the same direction as that of the non-linear strut.
In a method of manufacturing an electronic device by projecting a pattern onto a substrate by stitching a plurality of divided regions, if some of the plurality of regions form arcs, the throughput is increased and the device cost is reduced.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.